A thin-film transistor (TFT) is used as a switching element to be provided for not only each pixel in the display area of an active-matrix-addressed LCD but also its driver circuit as well. In the driver circuit, in particular, a CMOS (complementary metal oxide semiconductor) circuit is usually formed by two TFTs of mutually different conductivity types. In those applications, the TFTs should have even better performance and operate at even higher response speeds.
A conventional TFT, however, has rather high source-drain resistance, which is one of the factors causing deterioration in its device performance.
The source/drain regions of a TFT are usually defined by implanting dopant ions into a semiconductor film by ion doping process and then performing a heat treatment process to activate the ions implanted (which will be referred to herein as an “activating annealing process”). The activating annealing process is carried out to not only activate the ions of the element that have been implanted into the semiconductor film but also recover the degree of crystallinity that has decreased by going through the ion implantation process.
Examples of techniques for getting the activating annealing done include an annealing process using a normal furnace, a rapid thermal annealing (RTA) process, and a laser annealing process that uses a laser beam such as an excimer laser beam. The RTA process may be carried out either by using a UV or IR lamp or by increasing or decreasing the temperature of a substrate instantaneously by spraying a high-temperature inert gas onto the surface of the substrate.
Among these techniques, the furnace annealing process can be adopted if the substrate is a small glass motherboard but is difficult to apply to a situation where a glass substrate in as big a size as of more than 500 mm square is used. This is because the furnace annealing process usually causes a lot of thermal damage that would make the substrate shrink under the heat. On the other hand, the activation by laser annealing process uses the melting and solidifying process, and therefore, can activate the ions implanted efficiently. However, the laser annealing system itself is too expensive and complicated to ensure good stability in the manufacturing process. That is why considering the productivity and manufacturing cost, such an expensive and complicated system should not be used as a matter of principle unless it is absolutely necessary to use it to crystallize a semiconductor film, for example. For these reasons, as for low temperature polysilicon TFTs that are currently manufactured by a number of companies using a big glass substrate as a motherboard, the activation is usually done by RTA process. Nevertheless, if the activation is done by RTA annealing process, it is so difficult to activate the added element to be an acceptor efficiently enough as carriers in a p-type region, in particular, that only approximately 10% of the element can function as carriers according to current technologies.
Thus, according to the conventional method of defining source/drain regions, the element that has been added to the source/drain regions of a completed TFT has not been activated sufficiently and most of them cannot function as carriers (as is often the case with a p-channel TFT, among other things), thus increasing the source-drain resistance. If a lot of element to be donors and acceptors were added to the source/drain regions, then the resistance of the source/drain regions could be reduced, even though the degree of activation would still be low. But the productivity might decline in that case. On top of that, if a lot of dopant element were introduced, then the crystallinity of the semiconductor film could decrease too much to recover sufficiently by any kind of activating annealing process.
To overcome these problems, Patent Document No. 1 discloses a technique for defining source/drain regions by adding either a Group V element or a rare-gas element to a polycrystalline semiconductor film to turn it into an amorphous one, implanting ions of a dopant into the film to give it a predetermined conductivity type, and then activating the dopant ions by annealing process. According to this technique, crystallization of an amorphous phase can be used during the activating annealing process, and therefore, the dopant ions that have been implanted into the source/drain regions can be activated to a higher degree than what can be achieved by any other conventional technique.
Patent Document No. 1 also proposes that by adding either a Group IV element or a rare-gas element, only an upper portion of the semiconductor film be amorphized with the remaining lower portion thereof kept polycrystalline. According to such a technique, it says, the crystal grains that are present in the lower portion of the semiconductor film can be seed crystals, and therefore, the semiconductor film could recover a sufficiently high degree of crystallinity.
Hereinafter, such a technique for defining source/drain regions as taught by Patent Document No. 1 will be described with reference to FIGS. 1(A) through 1(C).
First, as shown in FIG. 1(A), ions 3 of a Group IV element or a rare-gas element are implanted into an upper portion of a polycrystalline Group IV semiconductor film 4 on the surface of a substrate 1. As a result, only that upper portion of the semiconductor film 4 gets amorphized to be an amorphous semiconductor layer 2A, while the lower portion of the semiconductor film 4 remains polycrystalline to be a polycrystalline semiconductor layer 2B.
Next, as shown in FIG. 1(B), the semiconductor film 4 is patterned into islands 4′ of semiconductor layer, and then a gate insulating film 9 and a gate electrode 10 are formed on each island 4′ of semiconductor layer. Thereafter, ions 5 of a dopant element to give a predetermined conductivity type are implanted into portions of each island 4′ of semiconductor layer to be source/drain regions.
Subsequently, as shown in FIG. 1(C), an activating annealing process is carried out to activate the dopant ions 5 implanted and recover the crystallinity of the islands 4′ of semiconductor layer using the semiconductor layer 2B as a seed crystal. In this manner, an island 6 of crystalline semiconductor layer is obtained. Those portions of the island of crystalline semiconductor layer 6 that have been implanted with the dopant ions 5 will be source/drain regions 7, while the other portion that has been masked with the gate electrode 10 and has not been implanted with the dopant ions 5 becomes a channel region 11.
Patent Document No. 1 discloses that defects may remain as residual defects in the region 8 to be an interface between the semiconductor layers 2A and 2B but that it is possible to prevent leakage current from flowing due to the presence of those residual defects by implanting the dopant ions 5 deeper beyond the region 8. In this case, “to implant the dopant ions 5 deeper beyond the region 8” means implanting the dopant ions 5 under such conditions that the depth of the region 8 will fall within the depth range of the dopant ions 5 that are implanted into the island 6 of crystalline semiconductor layer (i.e., so that the region 8 will form part of the portion of the island 6 of crystalline semiconductor layer that has been implanted with the dopant ions 5 (which will be referred to herein as an “dopant implanted region”)).                Patent Document No. 1: Japanese Patent Application Laid-Open Publication No. 2005-209978        